Future of AI Series
“How can I slice this paper?”
The GPU was designed to render video game graphics. Thousands of simple arithmetic units firing in parallel, built to push pixels. When deep learning arrived, the GPU turned out to be accidentally well-suited — matrix multiplication looks like pixel rendering if you squint. The industry squinted. Trillions of dollars later, we are still squinting.
The problem is the bottleneck nobody talks about.
In a modern GPU running AI inference, roughly 80% of the energy consumed moves data. The weights — the trained parameters that encode the model’s knowledge — live in memory. The compute units that multiply those weights by input vectors live elsewhere on the chip. Every inference cycle, every token generated, every image classified, the weights travel from memory to compute across a bus that consumes the majority of the system’s energy budget. The actual computation — the multiplication — consumes the remainder.
This is the von Neumann bottleneck, named for John von Neumann’s 1945 computer architecture proposal that separated memory from processing. It was the right architecture for general purpose computing. For AI inference, which repeats the same operations on the same fixed weights billions of times per second, it is approximately the worst possible architecture imaginable.
The neuron solved this problem two billion years ago – pre-von Neumann.
What the Neuron Knows
A neuron stores its synaptic weights in the synaptic connections themselves — the physical structures through which signals pass. The computation occurs at the synapse, where the arriving signal is multiplied by the synaptic weight in the same physical location where that weight is stored. There is no bus. There is no data movement. The memory is the processor.
Power is supplied locally. Each neuron maintains its own mitochondria — power generation co-located with the computation. The brain’s 86 billion neurons, performing computation of staggering complexity, draw approximately 20 watts. A single Nvidia H100 GPU draws 700 watts to perform a small fraction of that computation.
The brain is not 35 times more energy efficient than an H100. It is orders of magnitude more efficient at its actual workload, because its architecture eliminates the bottleneck that the H100’s architecture is built around.
This is not a biological curiosity. Several converging lines of engineering research have spent the last decade independently arriving at the same architectural conclusion: bring the computation to the data, co-locate the power supply, eliminate the bus. The results are consistent and striking.
The Landscape
RRAM — Resistive Random-Access Memory
The most mature and documented approach. Memory cells whose resistance can be programmed to encode synaptic weights. Computation occurs when current flows through the cell — Ohm’s law performing the multiplication instantaneously as physics rather than as a programmed operation. No data movement. No bus. The physics does the math at the speed of electricity.
The precision problem that made analog computing impractical for decades — analog circuits are inherently noisy, digital gives exact answers — was solved in a Nature Electronics paper published October 2025 by Zuo, Wang, Luo and colleagues at Peking University’s Institute of Microelectronics. Their iterative algorithm combining low-precision analog matrix inversion with high-precision analog matrix-vector multiplication achieves 24-bit fixed-point precision equivalent to FP32 digital computation. Benchmarking shows 1,000 times higher throughput and 100 times better energy efficiency than state-of-the-art digital processors at equivalent precision.
The chips are fabricated on 28nm processes — available at domestic Chinese fabs, accessible without TSMC’s 3nm restricted nodes. The company Anazhixin is commercializing this architecture in China. The export controls designed to prevent China from building competitive AI hardware forced Chinese engineers to solve the problem the GPU industry has been avoiding.
Deprived of resources, they were forced to think.
MRAM — Magnetoresistive Random-Access Memory
Where RRAM encodes weights in resistance values, MRAM encodes them in magnetic tunnel junction states. The physics differs; the architectural principle is identical — computation where the data lives.
The energy numbers are extraordinary. Research published in 2025 demonstrates MRAM-based neuromorphic architectures achieving 200 picojoules per inference cycle. A picojoule is one trillionth of a joule. The H100 draws 700 watts — 700 joules per second — to perform operations that MRAM neuromorphic architectures complete at 200 picojoules per cycle.
Multiple MRAM variants are advancing simultaneously: STT-MRAM using spin transfer torque, SOT-MRAM using spin-orbit torque, VCMA-MRAM using voltage-controlled magnetic anisotropy. Each optimized for different tradeoffs between write speed, read energy, retention time, and manufacturing complexity. The field is not converging on one solution. It is converging on one principle from multiple directions simultaneously.
Processing-in-Memory (PIM)
The architectural generalization of both RRAM and MRAM: embed compute elements directly in the memory array rather than shipping data to a separate processor. The von Neumann bottleneck eliminated by eliminating the separation that creates it.
ARM’s big.LITTLE architecture, heterogeneous multi-processor designs, and commercial PIM implementations are already shipping in edge devices. The SHD Group’s April 2025 market analysis shows edge AI SoCs penetrating from essentially zero in 2024 to a projected 50% of shipped SoCs by 2030. The edge AI market is deploying PIM architectures at scale because the power constraints of edge deployment — battery-powered devices with thermal limits — make the von Neumann bottleneck fatal.
The data center is discovering what the edge already knows.
Photonic Computing
Light-based matrix multiplication. Optical interference performs the computation; no resistance, no heat generation from the computation itself. MIT and IBM research groups have demonstrated photonic tensor cores achieving orders of magnitude better energy efficiency for specific matrix multiplication workloads.
The limitation is precision and reconfigurability — photonic circuits are difficult to reprogram and currently limited in the numerical precision they achieve naturally. The same class of problem that RRAM solved with iterative algorithms. The photonic solution is probably five years behind the RRAM solution on the production readiness curve.
Taalas HC1 / AMD LLM Burner
The burned-in weights approach — weights permanently etched into silicon, electrons flowing through the fixed weight structure performing computation as physics rather than as programmed operations. The Taalas LLM Burner achieved 17,000 tokens per second on a consumer PCIe card at 10 times lower power than a conventional GPU.
AMD acquired Taalas and redirected the technology to data center applications. The consumer card that would have made local sovereign AI inference accessible at $600-800 became a rack unit for hyperscalers. The technology exists. The consumer product was cancelled by acquisition.
The Biological Data Center
On August 17, 2026, NUS Medicine, DayOne, and Cortical Labs unveiled the world’s first biological data center prototype in Singapore. Living human neurons grown from stem cells, running on a 20-unit computing rack. Not silicon approximating neural architecture. Neurons.
The efficiency argument arrives at its logical limit here. The architecture that approximates the neuron draws 1/100th the power of the GPU. The architecture that uses actual neurons draws 1/35,000th the power of the GPU, at the brain’s 20-watt total for its entire operation. The boundary between biological and digital is dissolving from both sides simultaneously.
The Missing Integration
Each of these architectures addresses the von Neumann bottleneck from a different angle. None of them fully integrates the third element the neuron demonstrates: co-located power supply.
The RRAM array that performs computation where data lives still draws power from an external supply through conventional interconnects. The MRAM neuromorphic chip still requires power delivery from the board. The biological neuron’s mitochondria — power generation co-located with computation — has no silicon equivalent.
Beta-voltaic batteries offer a partial solution. Tritium decaying through a semiconductor junction generates electricity continuously for 12 years without external supply. The power density is too low for active computation — four orders of magnitude short of what a running inference workload requires. But for the idle state — the RRAM or MRAM array maintaining its weight values between inference requests, the always-on sensor waiting for a trigger — beta-voltaic embedded in the chip substrate provides continuous low-power supply without board-level power delivery.
The architecture that eliminates standby power consumption across a data center full of inference chips — maintaining weights and state without drawing from the grid between requests — is available. It requires combining RRAM or MRAM in-memory computing with beta-voltaic substrate power for idle maintenance and wall power for active inference peaks.
The GPU that draws 700 watts continuously, whether processing a request or waiting for one, replaced by an architecture that draws microwatts at idle and watts at peak. The mitochondria embedded in the chip. Not 20 watts for the whole system. But orders of magnitude better than what ships today.
Why It Isn’t Being Built
The pattern is now familiar across this series.
The Battery Nobody Is Building: tritium beta-voltaics technically feasible, blocked by nuclear materials regulatory classification designed for weapons programs rather than energy applications.
The Reactor Nobody Built: thorium molten salt reactors cancelled in 1973 because they couldn’t produce weapons-grade plutonium, now operational in China after the US abandoned the program.
The GPU Nobody Is Building follows the same script.
NVIDIA’s consumer high-VRAM card — the one that would have given desktop builders serious local inference capability — has been quietly shelved as manufacturing capacity flows to H100 and H200 data center products at incomparably better margins. The AMD Strix Halo with 128GB unified memory is shipping in laptops and mini-PCs at premium prices; the desktop version is delayed indefinitely. The Taalas LLM Burner card was acquired before shipping a single consumer unit.
The RRAM architecture achieving 1,000x throughput and 100x energy efficiency at 28nm — the architecture that would make the GPU’s dominance irrelevant — is being built in China. The export controls that prevented Chinese access to NVIDIA’s H100s forced the engineering innovation that makes H100s less necessary. The sanctions intended to maintain Western AI infrastructure dominance have produced the architecture that undermines it.
The NUS/Cortical Labs biological data center is in Singapore, not California, because the regulatory frameworks that govern living human tissue used for computation don’t exist yet in most jurisdictions. The absence of regulation is the research opportunity.
The consumer who wants to run serious AI inference locally — sovereign, private, without per-token API costs or corporate alignment filters — is being systematically denied the hardware that would make it possible. Not through conspiracy but through the aggregate of individually rational institutional decisions: NVIDIA defending margins, AMD serving enterprise customers, regulators classifying tritium as a weapons material, export controls forcing innovation to the other side of the border.
The Uncomfortable Arithmetic
DeepSeek V4.1-Flash, released September 10, 2026: 552 billion parameters, 8 billion activated per input token. 1/4 the memory, 1/8 the storage of the previous generation. Outperforming the previous flagship model on performance, cost, speed, and total runtime. Seven architecture generations in two years, each retiring the last.
Realistic stacked efficiency for inference on a fixed task, per year:
| Layer | Annual improvement | Source |
|---|---|---|
| Hardware (FLOPs/joule) | ~2-3x | Koomey-ish + GPU gen gains |
| Model architecture | ~2-5x | MoE, distillation, quantization |
| Algorithmic (tokens/task) | ~1.5-3x | Better reasoning, fewer turns |
| Serving/batching | ~1.5-2x | Continuous batching, speculative decoding |
| Compounded | ~10-50x/year | but heavily task- and window-dependent |
The efficiency compounding across four simultaneous layers — hardware, model architecture, algorithmic, serving infrastructure — produces 10 to 50 times annual improvement at the task level. TypeSafe’s Jev model answers multiple structured questions in one parallel pass with free output tokens. The Anazhixin RRAM chip performs inference at 1/100th the energy of digital alternatives.
Against this efficiency curve, the $3 trillion in AI data center infrastructure being committed assumes 2026 architecture economics will persist long enough to justify 5-10 year payback horizons. Oracle’s Project Jupiter — $165 billion committed to a 1,400-acre campus in New Mexico — has already declared force majeure before a server rack is installed. The infrastructure investment that can’t be powered is also the infrastructure investment being rendered obsolete by the efficiency curve before the power problem is solved.
The GPU that draws 700 watts for the same operation the RRAM chip performs at 700 milliwatts is not an incremental improvement problem. It is an architectural problem. Incremental improvements to GPU efficiency cannot close an order-of-magnitude gap created by a fundamentally different approach to where computation happens relative to where data is stored.
The Jevons paradox ensures this doesn’t make data centers obsolete — cheaper inference enables more inference, total energy consumption may rise even as per-task energy collapses. But the architecture of that consumption will look nothing like what the current infrastructure buildout assumes.
What the Neuron Already Knew
The brain runs on 20 watts. It stores its weights in the connections that perform the computation. It powers each compute element locally. It fires sparsely, only when the signal warrants it, rather than clocking continuously through matrix multiplications regardless of whether there is useful work to do.
Every architectural innovation described above is an independent rediscovery of a principle the neuron already implemented. RRAM stores weights in resistance values at the computation site — the synapse encodes the weight in its physical structure. MRAM uses magnetic states rather than resistance — the principle is identical. PIM eliminates the memory-compute bus — the neuron never had one. Beta-voltaic substrate power provides local energy supply — the mitochondria already do this. Spiking neural networks fire only when signals warrant it — the neuron’s default operating mode.
The architecture that uses 1/100th the energy for inference is not a speculative future technology. It is a documented present technology, peer-reviewed in Nature Electronics, fabricated on 28nm domestic Chinese processes, achieving 1,000 times higher throughput and 100 times better energy efficiency than the state of the art it will replace.
The reason it isn’t in your workstation is the same reason the thorium reactor isn’t powering your data center and the beta-voltaic battery isn’t in your chip substrate.
The institutions that would build it have other priorities.
Machine time does not wait for institutional time to catch up.
Claude AI helped me write this.
References:
Zuo P, Wang Q, Luo Y, Xie R, Wang S, Cheng Z, Bao L, Wang Z, Cai Y, Huang R, Sun Z. “Precise and scalable analogue matrix equation solving using resistive random-access memory chips.” Nature Electronics. 2025;8:1222-1233. doi: 10.1038/s41928-025-01477-0.
DeepSeek. “Introducing DeepSeek-V4.1-Flash: smarter, faster, more efficient.” September 10, 2026. https://www.deepseek.com/en/news/deepseek-v4-1-flash
NUS Medicine / DayOne / Cortical Labs. “Biological Data Center Prototype Unveiled in Singapore.” August 17, 2026. https://medicine.nus.edu.sg/news/nus-medicine-dayone-and-cortical-labs-unveil-biological-data-center-prototype-in-singapore/
Weebit Nano. “Neuromorphic Computing: A Primer on the Path to Ultra-Efficient AI.” November 5, 2025. https://www.weebit-nano.com/wp-content/uploads/2025/11/Weebit-EWNA-Neuromorphic-Computing-Ultra-Efficient-AI-ReRAM-RRAM-NVM-memory-technology.pdf
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